CVE-2026-43191 (GCVE-0-2026-43191)

Vulnerability from cvelistv5 – Published: 2026-05-06 11:28 – Updated: 2026-05-07 17:14
VLAI?
Title
drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35
Summary
In the Linux kernel, the following vulnerability has been resolved: drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35 [Why] A backport of the change made for DCN401 that addresses an issue where we turn off the PHY PLL when disabling TMDS output, which causes the OTG to remain stuck. The OTG being stuck can lead to a hang in the DCHVM's ability to ACK invalidations when it thinks the HUBP is still on but it's not receiving global sync. The transition to PLL_ON needs to be atomic as there's no guarantee that the thread isn't pre-empted or is able to complete before the IOMMU watchdog times out. [How] Backport the implementation from dcn401 back to dcn35. There's a functional difference in when the eDP output is disabled in dcn401 code so we don't want to utilize it directly.
Severity ?
No CVSS data available.
Assigner
References
Impacted products
Vendor Product Version
Linux Linux Affected: ec129fa356bea5411cb16833cc5dab32689ea389 , < d1f7ceb00e8956ff6d183b7b45ef4e73c96f4c51 (git)
Affected: ec129fa356bea5411cb16833cc5dab32689ea389 , < 75372d75a4e23783583998ed99d5009d555850da (git)
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    Linux Linux Affected: 6.7
Unaffected: 0 , < 6.7 (semver)
Unaffected: 6.19.6 , ≤ 6.19.* (semver)
Unaffected: 7.0 , ≤ * (original_commit_for_fix)
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{
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          "programFiles": [
            "drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c",
            "drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h",
            "drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c"
          ],
          "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
          "vendor": "Linux",
          "versions": [
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              "versionType": "git"
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            "drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h",
            "drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c"
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          "value": "In the Linux kernel, the following vulnerability has been resolved:\n\ndrm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35\n\n[Why]\nA backport of the change made for DCN401 that addresses an issue where\nwe turn off the PHY PLL when disabling TMDS output, which causes the\nOTG to remain stuck.\n\nThe OTG being stuck can lead to a hang in the DCHVM\u0027s ability to ACK\ninvalidations when it thinks the HUBP is still on but it\u0027s not receiving\nglobal sync.\n\nThe transition to PLL_ON needs to be atomic as there\u0027s no guarantee\nthat the thread isn\u0027t pre-empted or is able to complete before the\nIOMMU watchdog times out.\n\n[How]\nBackport the implementation from dcn401 back to dcn35.\n\nThere\u0027s a functional difference in when the eDP output is disabled in\ndcn401 code so we don\u0027t want to utilize it directly."
        }
      ],
      "providerMetadata": {
        "dateUpdated": "2026-05-07T17:14:38.021Z",
        "orgId": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
        "shortName": "Linux"
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          "url": "https://git.kernel.org/stable/c/75372d75a4e23783583998ed99d5009d555850da"
        }
      ],
      "title": "drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35",
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    "assignerShortName": "Linux",
    "cveId": "CVE-2026-43191",
    "datePublished": "2026-05-06T11:28:00.470Z",
    "dateReserved": "2026-05-01T14:12:55.992Z",
    "dateUpdated": "2026-05-07T17:14:38.021Z",
    "state": "PUBLISHED"
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      "percentile": "0.05025"
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  }
}


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