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    <lastBuildDate>Wed, 07 Oct 2026 04:09:38 +0000</lastBuildDate>
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      <title>CVE-2024-47667 — PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)</title>
      <link>https://vulnerability.circl.lu/vuln/cve-2024-47667</link>
      <description>&lt;p&gt;&lt;strong&gt;Affected:&lt;/strong&gt; Linux&lt;/p&gt;
&lt;p&gt;In the Linux kernel, the following vulnerability has been resolved:&lt;/p&gt;
&lt;p&gt;PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)&lt;/p&gt;
&lt;p&gt;Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
(SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
the bus may corrupt the packet payload and the corrupt data may
cause associated applications or the processor to hang.&lt;/p&gt;
&lt;p&gt;The workaround for Errata #i2037 is to limit the maximum read
request size and maximum payload size to 128 bytes. Add workaround
for Errata #i2037 here.&lt;/p&gt;
&lt;p&gt;The errata and workaround is applicable only to AM65x SR 1.0 and
later versions of the silicon will have this fixed.&lt;/p&gt;
&lt;p&gt;[1] -&amp;gt; https://www.ti.com/lit/er/sprz452i/sprz452i.pdf&lt;/p&gt;</description>
      <content:encoded>&lt;p&gt;&lt;strong&gt;Affected:&lt;/strong&gt; Linux&lt;/p&gt;
&lt;p&gt;In the Linux kernel, the following vulnerability has been resolved:&lt;/p&gt;
&lt;p&gt;PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)&lt;/p&gt;
&lt;p&gt;Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
(SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
the bus may corrupt the packet payload and the corrupt data may
cause associated applications or the processor to hang.&lt;/p&gt;
&lt;p&gt;The workaround for Errata #i2037 is to limit the maximum read
request size and maximum payload size to 128 bytes. Add workaround
for Errata #i2037 here.&lt;/p&gt;
&lt;p&gt;The errata and workaround is applicable only to AM65x SR 1.0 and
later versions of the silicon will have this fixed.&lt;/p&gt;
&lt;p&gt;[1] -&amp;gt; https://www.ti.com/lit/er/sprz452i/sprz452i.pdf&lt;/p&gt;</content:encoded>
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