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  <updated>2026-09-30T15:23:14.771145+00:00</updated>
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  <entry>
    <id>https://vulnerability.circl.lu/vuln/cve-2022-50370</id>
    <title>CVE-2022-50370 — i2c: designware: Fix handling of real but unexpected device interrupts</title>
    <updated>2026-09-30T15:23:14.772776+00:00</updated>
    <content type="xhtml">
      <div xmlns="http://www.w3.org/1999/xhtml"><p><strong>Affected:</strong> Linux</p>
<p>In the Linux kernel, the following vulnerability has been resolved:</p>
<p>i2c: designware: Fix handling of real but unexpected device interrupts</p>
<p>Commit c7b79a752871 ("mfd: intel-lpss: Add Intel Alder Lake PCH-S PCI
IDs") caused a regression on certain Gigabyte motherboards for Intel
Alder Lake-S where system crashes to NULL pointer dereference in
i2c_dw_xfer_msg() when system resumes from S3 sleep state ("deep").</p>
<p>I was able to debug the issue on Gigabyte Z690 AORUS ELITE and made
following notes:</p>
<p>- Issue happens when resuming from S3 but not when resuming from
  "s2idle"
- PCI device 00:15.0 == i2c_designware.0 is already in D0 state when
  system enters into pci_pm_resume_noirq() while all other i2c_designware
  PCI devices are in D3. Devices were runtime suspended and in D3 prior
  entering into suspend
- Interrupt comes after pci_pm_resume_noirq() when device interrupts are
  re-enabled
- According to register dump the interrupt really comes from the
  i2c_designware.0. Controller is enabled, I2C target address register
  points to a one detectable I2C device address 0x60 and the
  DW_IC_RAW_INTR_STAT register START_DET, STOP_DET, ACTIVITY and
  TX_EMPTY bits are set indicating completed I2C transaction.</p>
<p>My guess is that the firmware uses this controller to communicate with
an on-board I2C device during resume but does not disable the controller
before giving control to an operating system.</p>
<p>I was told the UEFI update fixes this but never the less it revealed the
driver is…</p></div>
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    <link href="https://vulnerability.circl.lu/vuln/cve-2022-50370"/>
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