{"@ID": "1419", "@Name": "Incorrect Initialization of Resource", "@Abstraction": "Class", "@Structure": "Simple", "@Status": "Incomplete", "Description": "The product attempts to initialize a resource but does not correctly do so, which might leave the resource in an unexpected, incorrect, or insecure state when it is accessed.", "Extended_Description": {"xhtml:p": ["This can have security implications when the associated resource is expected to have certain properties or values. Examples include a variable that determines whether a user has been authenticated or not, or a register or fuse value that determines the security state of the product.", "For software, this weakness can frequently occur when implicit initialization is used, meaning the resource is not explicitly set to a specific value. For example, in C, memory is not necessarily cleared when it is allocated on the stack, and many scripting languages use a default empty, null value, or zero value when a variable is not explicitly initialized.", "For hardware, this weakness frequently appears with reset values and fuses. After a product reset, hardware may initialize registers incorrectly. During different phases of a product lifecycle, fuses may be set to incorrect values. Even if fuses are set to correct values, the lines to the fuse could be broken or there might be hardware on the fuse line that alters the fuse value to be incorrect."]}, "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "665", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": [{"Ordinality": "Primary"}, {"Ordinality": "Resultant"}]}, "Applicable_Platforms": {"Language": {"@Class": "Not Language-Specific", "@Prevalence": "Undetermined"}, "Operating_System": {"@Class": "Not OS-Specific", "@Prevalence": "Undetermined"}, "Architecture": {"@Class": "Not Architecture-Specific", "@Prevalence": "Undetermined"}, "Technology": {"@Class": "Not Technology-Specific", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": [{"Phase": "Implementation"}, {"Phase": "Manufacturing"}, {"Phase": "Installation"}, {"Phase": "System Configuration"}, {"Phase": "Operation"}]}, "Common_Consequences": {"Consequence": [{"Scope": "Confidentiality", "Impact": ["Read Memory", "Read Application Data", "Unexpected State"], "Likelihood": "Unknown"}, {"Scope": ["Authorization", "Integrity"], "Impact": "Gain Privileges or Assume Identity"}, {"Scope": "Other", "Impact": "Varies by Context", "Note": "The technical impact can vary widely based on how the resource is used in the product, and whether its contents affect security decisions."}]}, "Detection_Methods": {"Detection_Method": {"@Detection_Method_ID": "DM-14", "Method": "Automated Static Analysis", "Description": "Automated static analysis, commonly referred to as Static Application Security Testing (SAST), can find some instances of this weakness by analyzing source code (or binary/compiled code) without having to execute it. Typically, this is done by building a model of data flow and control flow, then searching for potentially-vulnerable patterns that connect \"sources\" (origins of input) with \"sinks\" (destinations where the data interacts with external components, a lower layer such as the OS, etc.)"}}, "Potential_Mitigations": {"Mitigation": [{"Phase": "Implementation", "Description": "Choose the safest-possible initialization for security-related resources."}, {"Phase": "Implementation", "Description": "Ensure that each resource (whether variable, memory buffer, register, etc.) is fully initialized."}, {"Phase": "Implementation", "Description": "Pay close attention to complex conditionals or reset sources   that affect initialization, since some paths might not perform the initialization."}, {"Phase": "Architecture and Design", "Description": "Ensure that the design and architecture clearly identify what the initialization should be, and that the initialization does not have security implications."}]}, "Demonstrative_Examples": {"Demonstrative_Example": [{"@Demonstrative_Example_ID": "DX-162", "Intro_Text": "Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "Data_out <= REGISTER_DEFAULT; // Register content set to Default at reset \n\t\t\t\t\t  Secure_mode <= REGISTER_DEFAULT[0]; // Register Secure_mode set at reset"}, {"@style": "margin-left:1em;", "xhtml:br": null, "#text": "Data_out <= Data_in;"}], "#text": "if (~resetn) \n\t\t\t\t\tbegin \n\t\t\t\t\t\n\t\t\t\t\tend \n\t\t\t\t\telse if (write & ~Secure_mode) \n\t\t\t\t\tbegin \n\t\t\t\t\t\n\t\t\t\t\tend"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": ".REGISTER_WIDTH (32), \n\t\t\t\t\t.REGISTER_DEFAULT (1224) // Incorrect Default value used bit 0 is 0."}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".Data_in (Data_in), \n\t\t\t\t\t.Data_out (Secure_reg), \n\t\t\t\t\t.Clk (Clk), \n\t\t\t\t\t.resetn (resetn), \n\t\t\t\t\t.write (write)"}, {"@style": "margin-left:1em;", "xhtml:br": null, "#text": ".REGISTER_WIDTH (32) // Default not defined 2^32-2 value will be used as default."}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".Data_in (Data_in), \n\t\t\t\t\t.Data_out (Insecure_reg), \n\t\t\t\t\t.Clk (Clk), \n\t\t\t\t\t.resetn (resetn), \n\t\t\t\t\t.write (write)"}], "#text": "// Parameterized Register module example \n\t\t\t\t  // Secure_mode : REGISTER_DEFAULT[0] : When set to 1 register is read only and not writable// \n\t\t\t\t  module register_example \n\t\t\t\t  #( \n\t\t\t\t  parameter REGISTER_WIDTH = 8, // Parameter defines width of register, default 8 bits \n\t\t\t\t  parameter [REGISTER_WIDTH-1:0] REGISTER_DEFAULT = 2**REGISTER_WIDTH -2 // Default value of register computed from Width. Sets all bits to 1s except bit 0 (Secure _mode) \n\t\t\t\t  ) \n\t\t\t\t  ( \n\t\t\t\t  input [REGISTER_WIDTH-1:0] Data_in, \n\t\t\t\t  input Clk, \n\t\t\t\t  input resetn, \n\t\t\t\t  input write, \n\t\t\t\t  output reg [REGISTER_WIDTH-1:0] Data_out \n\t\t\t\t  ); \n\t\t\t\t  \n\t\t\t\t  reg Secure_mode; \n\t\t\t\t  \n\t\t\t\t  always @(posedge Clk or negedge resetn) \n\t\t\t\t  \n\t\t\t\t  endmodule \n                  \n                  \n\t\t\t\t  module register_top \n\t\t\t\t  ( \n\t\t\t\t  input Clk, \n\t\t\t\t  input resetn, \n\t\t\t\t  input write, \n\t\t\t\t  input [31:0] Data_in, \n\t\t\t\t  output reg [31:0] Secure_reg, \n\t\t\t\t  output reg [31:0] Insecure_reg \n\t\t\t\t  ); \n\t\t\t\t  \n\t\t\t\t  register_example #( \n\t\t\t\t  \n\t\t\t\t  ) Insecure_Device_ID_1 ( \n\t\t\t\t  \n\t\t\t\t  ); \n                  \n\t\t\t\t  register_example #(\n\t\t\t\t  \n\t\t\t\t  ) Insecure_Device_ID_2 ( \n\t\t\t\t  \n\t\t\t\t  ); \n                  \n\t\t\t\t  endmodule"}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": ".REGISTER_WIDTH (32), \n\t\t\t\t\t.REGISTER_DEFAULT (1225) // Correct default value set, to enable Secure_mode"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null], "#text": ".Data_in (Data_in), \n\t\t\t\t\t.Data_out (Secure_reg), \n\t\t\t\t\t.Clk (Clk), \n\t\t\t\t\t.resetn (resetn), \n\t\t\t\t\t.write (write)"}], "#text": "register_example #( \n\t\t\t\t  \n\t\t\t\t  ) Secure_Device_ID_example ( \n\t\t\t\t  \n\t\t\t\t  );"}], "Body_Text": ["These example instantiations show how, in a hardware design, it would be possible to instantiate the register module with insecure defaults and parameters.", "In the example design, both registers will be software writable since Secure_mode is defined as zero."]}, {"@Demonstrative_Example_ID": "DX-163", "Intro_Text": "This code attempts to login a user using credentials from a POST request:", "Example_Code": [{"@Nature": "Bad", "@Language": "PHP", "xhtml:div": {"xhtml:br": [null, null, null, null, null], "xhtml:i": ["// $user and $pass automatically set from POST request", "..."], "xhtml:div": [{"@style": "margin-left:1em;", "#text": "$authorized = true;"}, {"@style": "margin-left:1em;", "#text": "generatePage();"}], "#text": "if (login_user($user,$pass)) {}\n                    \n                    \n                  if ($authorized) {}"}}, {"@Nature": "Good", "@Language": "PHP", "xhtml:div": {"xhtml:br": [null, null, null, null, null], "xhtml:div": {"@style": "margin-left:1em;", "#text": "$authorized = true;"}, "xhtml:i": "...", "#text": "$user = $_POST['user'];$pass = $_POST['pass'];$authorized = false;if (login_user($user,$pass)) {}"}}], "Body_Text": ["Because the $authorized variable is never initialized, PHP will automatically set $authorized to any value included in the POST request if register_globals is enabled. An attacker can send a POST request with an unexpected third value 'authorized' set to 'true' and gain authorized status without supplying valid credentials.", "Here is a fixed version:", "This code avoids the issue by initializing the $authorized variable to false and explicitly retrieving the login credentials from the $_POST variable. Regardless, register_globals should never be enabled and is disabled by default in current versions of PHP."]}, {"@Demonstrative_Example_ID": "DX-222", "Intro_Text": "The following example code is excerpted from the Access Control module, acct_wrapper, in the Hack@DAC'21 buggy OpenPiton System-on-Chip (SoC). Within this module, a set of memory-mapped I/O registers, referred to as acct_mem, each 32-bit wide, is utilized to store access control permissions for peripherals [REF-1437]. Access control registers are typically used to define and enforce permissions and access rights for various system resources.", "Body_Text": ["However, in the buggy SoC, these registers are all enabled at reset, i.e., essentially granting unrestricted access to all system resources [REF-1438]. This will introduce security vulnerabilities and risks to the system, such as privilege escalation or exposing sensitive information to unauthorized users or processes.", "To fix this issue, the access control registers must be properly initialized during the reset phase of the SoC. Correct initialization values should be established to maintain the system's integrity, security, predictable behavior, and allow proper control of peripherals. The specifics of what values should be set depend on the SoC's design and the requirements of the system. To address the problem depicted in the bad code example [REF-1438], the default value for \"acct_mem\" should be set to 32'h00000000 (see good code example [REF-1439]). This ensures that during startup or after any reset, access to protected data is restricted until the system setup is complete and security procedures properly configure the access control settings."], "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:b": "acct_mem[j] <= 32'hffffffff;", "xhtml:br": null}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\tend"}, "#text": "for (j=0; j < AcCt_MEM_SIZE; j=j+1)"}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\tend"}, "#text": "if(~(rst_ni && ~rst_6))"}, "#text": "begin\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t..."}, "#text": "always @(posedge clk_i)"}, "#text": "module acct_wrapper #(\n\t\t\t\t\t\t..."}, {"@Nature": "Good", "@Language": "Verilog", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": null, "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:b": "acct_mem[j] <= 32'h00000000;", "xhtml:br": null}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\tend"}, "#text": "for (j=0; j < AcCt_MEM_SIZE; j=j+1)"}, "#text": "begin\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\tend"}, "#text": "if(~(rst_ni && ~rst_6))"}, "#text": "begin\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t..."}, "#text": "always @(posedge clk_i)"}, "#text": "module acct_wrapper #(\n\t\t\t\t\t\t..."}]}]}, "Observed_Examples": {"Observed_Example": [{"Reference": "CVE-2020-27211", "Description": "Chain: microcontroller system-on-chip uses a register value stored in flash to set product protection state on the memory bus and does not contain protection against fault injection (CWE-1319) which leads to an incorrect initialization of the memory bus (CWE-1419) causing the product to be in an unprotected state.", "Link": "https://www.cve.org/CVERecord?id=CVE-2020-27211"}, {"Reference": "CVE-2023-25815", "Description": "chain: a change in an underlying package causes the gettext function to use implicit initialization with a hard-coded path (CWE-1419) under the user-writable C:\\ drive, introducing an untrusted search path element (CWE-427) that enables spoofing of messages.", "Link": "https://www.cve.org/CVERecord?id=CVE-2023-25815"}, {"Reference": "CVE-2022-43468", "Description": "WordPress module sets internal variables based on external inputs, allowing false reporting of the number of views", "Link": "https://www.cve.org/CVERecord?id=CVE-2022-43468"}, {"Reference": "CVE-2022-36349", "Description": "insecure default variable initialization in BIOS firmware for a hardware board allows DoS", "Link": "https://www.cve.org/CVERecord?id=CVE-2022-36349"}, {"Reference": "CVE-2015-7763", "Description": "distributed filesystem only initializes part of the variable-length padding for a packet, allowing attackers to read sensitive information from previously-sent packets in the same memory location", "Link": "https://www.cve.org/CVERecord?id=CVE-2015-7763"}]}, "References": {"Reference": [{"@External_Reference_ID": "REF-1437"}, {"@External_Reference_ID": "REF-1438"}, {"@External_Reference_ID": "REF-1439"}]}, "Mapping_Notes": {"Usage": "Allowed-with-Review", "Rationale": "This CWE entry is a Class and might have Base-level children that would be more appropriate", "Comments": "Examine children of this entry to see if there is a better fit", "Reasons": {"Reason": {"@Type": "Abstraction"}}}, "Content_History": {"Submission": {"Submission_Name": "CWE Content Team", "Submission_Organization": "MITRE", "Submission_Date": "2023-10-11", "Submission_Version": "4.13", "Submission_ReleaseDate": "2023-10-26"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2024-07-16", "Modification_Version": "4.15", "Modification_ReleaseDate": "2024-07-16", "Modification_Comment": "updated Demonstrative_Examples, References"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Detection_Factors, Weakness_Ordinalities"}], "Contribution": [{"@Type": "Content", "Contribution_Name": "Anonymous External Contributor", "Contribution_Date": "2023-10-13", "Contribution_Comment": "Provided HW specific comments for Extended Description"}, {"@Type": "Content", "Contribution_Name": "Mohan Lal", "Contribution_Organization": "NVIDIA", "Contribution_Date": "2023-10-13", "Contribution_Comment": "Provided HW specific comments for Extended Description"}, {"@Type": "Content", "Contribution_Name": "Chen Chen, Rahul Kande, Jeyavijayan Rajendran", "Contribution_Organization": "Texas A&M University", "Contribution_Date": "2023-11-07", "Contribution_Comment": "suggested demonstrative example"}, {"@Type": "Content", "Contribution_Name": "Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi", "Contribution_Organization": "Technical University of Darmstadt", "Contribution_Date": "2023-11-07", "Contribution_Comment": "suggested demonstrative example"}]}}