{"@ID": "1223", "@Name": "Race Condition for Write-Once Attributes", "@Abstraction": "Base", "@Structure": "Simple", "@Status": "Incomplete", "Description": "A write-once register in hardware design is programmable by an untrusted software component earlier than the trusted software component, resulting in a race condition issue.", "Extended_Description": {"xhtml:p": ["Integrated circuits and hardware IP software programmable controls and settings are commonly stored in register circuits. These register contents have to be initialized at hardware reset to defined default values that are hard coded in the hardware description language (HDL) code of the hardware unit. A common security protection method used to protect register settings from modification by software is to make them write-once. This means the hardware implementation only allows writing to such registers once, and they become read-only after having been written once by software. This is useful to allow initial boot software to configure systems settings to secure values while blocking runtime software from modifying such hardware settings.", "Implementation issues in hardware design of such controls can expose such registers to a race condition security flaw. For example, consider a hardware design that has two different software/firmware modules executing in parallel. One module is trusted (module A) and another is untrusted (module B). In this design it could be possible for Module B to send write cycles to the write-once register before Module A. Since the field is write-once the programmed value from Module A will be ignored and the pre-empted value programmed by Module B will be used by hardware."]}, "Related_Weaknesses": {"Related_Weakness": {"@Nature": "ChildOf", "@CWE_ID": "362", "@View_ID": "1000", "@Ordinal": "Primary"}}, "Weakness_Ordinalities": {"Weakness_Ordinality": {"Ordinality": "Primary"}}, "Applicable_Platforms": {"Language": [{"@Name": "Verilog", "@Prevalence": "Undetermined"}, {"@Name": "VHDL", "@Prevalence": "Undetermined"}], "Technology": {"@Class": "System on Chip", "@Prevalence": "Undetermined"}}, "Modes_Of_Introduction": {"Introduction": {"Phase": "Architecture and Design", "Note": "This weakness can appear in designs that use register write-once attributes with two or more software/firmware modules with varying levels of trust executing in parallel."}}, "Common_Consequences": {"Consequence": {"Scope": "Access Control", "Impact": "Bypass Protection Mechanism", "Note": "System configuration cannot be programmed in a secure way."}}, "Detection_Methods": {"Detection_Method": {"Method": "Automated Analysis", "Description": "The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros."}}, "Potential_Mitigations": {"Mitigation": {"Phase": "Architecture and Design", "Description": "During hardware design, all register write-once or sticky fields must be evaluated for proper configuration."}}, "Demonstrative_Examples": {"Demonstrative_Example": {"Intro_Text": "Consider the example design module system Verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status value.", "Example_Code": [{"@Nature": "Bad", "@Language": "Verilog", "xhtml:br": [null, null, null, null, null, null, null, null, null, null, null], "xhtml:div": [{"@style": "margin-left:1em;", "xhtml:br": [null, null, null, null, null, null], "#text": "input [15:0] Data_in,\n                          input Clk,\n                          input ip_resetn,\n                          input global_resetn,\n                          input write,\n                          output reg [15:0] Data_out"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "Data_out <= 16'h0000; \n\t\t\t\t\t\t\tWrite_once_status <= 1'b0;"}, "#text": "begin\n\t\t\t\t\t\t  \n\t\t\t\t\t\t  end"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "Data_out <= Data_in & 16'hFFFE; // Input data written to register after masking bit 0\n\t\t\t\t\t\t\tWrite_once_status <= 1'b1; // Write once status set after first write."}, "#text": "begin\n\t\t\t\t\t\t  \n\t\t\t\t\t\t  end"}, {"@style": "margin-left:1em;", "xhtml:br": [null, null], "xhtml:div": {"@style": "margin-left:1em;", "xhtml:br": [null, null], "#text": "Data_out[15:1] <= Data_out[15:1];\n\t\t\t\t\t\t\tData_out[0] <= Write_once_status;"}, "#text": "begin\n\t\t\t\t\t\t  \n                          end"}], "#text": "module register_write_once_example\n                        (\n\t\t\t\t\t\t\n                        );\n                        \n                        reg Write_once_status;\n                        \n                        always @(posedge Clk or negedge ip_resetn)\n                        if (~ip_resetn)\n\t\t\t\t\t\t\n                        else if (write & ~Write_once_status) \n\t\t\t\t\t\t\n\t\t\t\t\t\telse if (~write)\n\t\t\t\t\t\t\n\t\t\t\t\t\tendmodule"}, {"@Nature": "Good", "@Language": "Other", "xhtml:ul": {"xhtml:li": ["Must confirm the Write_once_status (bit 0) value is zero, before programming register. If another agent has programmed the register before, then Write_once_status value will be one.", "After writing to the register, the trusted software can issue a read to confirm that the valid setting has been programmed."]}, "#text": "Trusted firmware or software trying to set the write-once field:"}], "Body_Text": "The first system component that sends a write cycle to this register can program the value. This could result in a race condition security issue in the SoC design, if an untrusted agent is running in the system in parallel with the trusted component that is expected to program the register."}}, "Related_Attack_Patterns": {"Related_Attack_Pattern": {"@CAPEC_ID": "26"}}, "Mapping_Notes": {"Usage": "Allowed", "Rationale": "This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.", "Comments": "Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.", "Reasons": {"Reason": {"@Type": "Acceptable-Use"}}}, "Content_History": {"Submission": {"Submission_Name": "Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi", "Submission_Organization": "Intel Corporation", "Submission_Date": "2019-12-12", "Submission_Version": "4.0", "Submission_ReleaseDate": "2020-02-24"}, "Modification": [{"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2020-08-20", "Modification_Version": "4.2", "Modification_ReleaseDate": "2020-08-20", "Modification_Comment": "updated Related_Attack_Patterns"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2022-10-13", "Modification_Version": "4.9", "Modification_ReleaseDate": "2022-10-13", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-04-27", "Modification_Version": "4.11", "Modification_ReleaseDate": "2023-04-27", "Modification_Comment": "updated Relationships"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2023-06-29", "Modification_Version": "4.12", "Modification_ReleaseDate": "2023-06-29", "Modification_Comment": "updated Mapping_Notes"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-04-03", "Modification_Version": "4.17", "Modification_ReleaseDate": "2025-04-03", "Modification_Comment": "updated Demonstrative_Examples"}, {"Modification_Name": "CWE Content Team", "Modification_Organization": "MITRE", "Modification_Date": "2025-12-11", "Modification_Version": "4.19", "Modification_ReleaseDate": "2025-12-11", "Modification_Comment": "updated Detection_Factors, Potential_Mitigations, Weakness_Ordinalities"}]}}